1. Field of the Invention
The present invention relates to a semiconductor device having a structure that an insulating film is formed as a spacer on an outer wall surface of a connection wiring layer and a method of manufacturing the same.
2. Description of the Related Art
A technique has been developed for forming a spacer insulating film on an outer wall surface of a connection wiring layer in order that a structural contact (short circuit) or electrical interaction may be prevented between connecting wiring layers adjacent to each other. For example, JP-A-6-310612 discloses a technique preventing contact between wiring layers or between the wiring layer and the substrate by an insulating film provided around the wiring layer and restraining a reduction in the reliability due to corrosion. Furthermore, the insulating film is formed by a chemical vapor deposition (CVD) process so that not only an upper surface of the wiring layer but also side faces and underside of the wiring layer are covered, whereby an effective insulating structure is provided.
On the other hand, a semiconductor device such as a non-volatile memory device is divided into a memory cell region and a peripheral circuit region. Memory cell arrays are arranged in the memory cell region, whereas peripheral circuits for driving the memory cell arrays are formed in the peripheral circuit region.
A large number of electrical components (corresponding to a conductive layer) are arranged in the memory cell region. Accordingly, intervals between adjacent memory cells in the memory cell region are smaller as compared with those in the peripheral circuit region and the electrical components in the memory cell region has a higher degree of integration as compared with the peripheral circuit region. On the other hand, since electrical components are spaced farther away from each other in the peripheral circuit region, the electrical components in the peripheral circuit region has a lower degree of integration.
With reduction in design rules, a desired insulating performance needs to be maintained between the electrical components in the memory cell region having a higher integration degree, whereas a desired insulating performance also needs to be maintained between the electrical components in the peripheral circuit region having a lower integration degree.